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MAX6948B
High-Efficiency PWM LED Driver with Boost
Converter and Five Constant-Current GPIO Ports
RST Input
The active-low RST input operates as a reset that voids
any current I 2 C transaction involving the MAX6948B,
forcing the device into the I 2 C STOP condition. Use the
D6 bit in the configuration register (Table 2) to configure
RST to reset all the internal registers to the power-on-
reset state (Table 3). The RST input is overvoltage toler-
ant to 5.5V.
The MAX6948B ignores all I 2 C bus activity while RST
remains low. The device uses this feature to minimize
supply current in power-critical applications by effective-
ly disconnecting the MAX6948B from the bus during idle
periods. RST also operates as a bus multiplexer, allow-
ing multiple devices to use the same I 2 C slave address.
Drive only one MAX6948B RST input high at any time to
use RST as a bus multiplexer.
The MAX6948B features a reset-run option. Taking the
RST input high brings the driver out of shutdown in addi-
tion to its normal function of enabling the device’s I 2 C
interface.
Reset-Run Option
The MAX6948B features a reset-run option enabling RST
to bring the driver out of shutdown, in addition to its nor-
mal function of enabling the MAX6948B’s I 2 C interface.
This provides an alternative method of bringing the driver
out of shutdown to writing to the configuration register
through the serial interface. The reset-run timing uses the
internal PWM clock.
After enabling the reset-run option, the MAX6948B uses
the rising edge on RST , followed by no I 2 C interface activ-
ity to the MAX6948B for 128 to 129 periods of the GPIO
PWM clock (32kHz typ) to trigger the reset-run option.
If this timeout period elapses without the MAX6948B
acknowledging an I 2 C transaction, the device sets the
run bit (D0) in the configuration register and brings itself
out of shutdown, activating any programmed ramp-up.
If RST pulses high for less than this timeout period to
trigger a reset run, the MAX6948B ignores the pulse and
continues to wait for a suitable trigger.
Cancel the reset-run trigger by transmitting an I 2 C com-
munication to the MAX6948B before the timeout period
elapses. The trigger cancels when the MAX6948B
acknowledges the I 2 C transaction and requires send-
ing at least the MAX6948B’s I 2 C slave address. The
minimum timeout period is equal to 4ms. The minimum
I 2 C clock speed that guarantees a successful start bit
and 8 data bits (9 bits total) within the minimum timeout
period is 9/4ms equal to 2.25kHz. Canceling the reset-
run trigger clears the reset-run bit (D1) in the configura-
tion register, disabling reset run. The run bit (D0) in the
configuration register remains cleared and the driver
remains in shutdown.
P2, P3, P4
P0, P1
P2, P3, P4 P0, P1
CURRENT CURRENT PORT CURRENT = FULL
CURRENT CURRENT
10mA 30mA
GLOBAL CURRENT = 0x07
10mA
30mA
8.75mA 26.25mA
7.5mA
22.5mA
6.25mA 18.75mA
GLOBAL CURRENT = 0x06
GLOBAL CURRENT = 0x05
GLOBAL CURRENT = 0x04
5mA
15mA
PORT CURRENT = HALF
5mA
15mA
GLOBAL CURRENT = 0x03
3.75mA 11.25mA
GLOBAL CURRENT = 0x02
2.5mA
7.5mA
GLOBAL CURRENT = 0x01
0mA
0mA
FULL 7/8
CURRENT CURRENT
RAMP-UP
6/8
CURRENT
5/8
CURRENT
4/8
CURRENT
3/8
CURRENT
2/8
CURRENT
RAMP-DOWN
1/8
CURRENT
ZERO
CURRENT
1.25mA
0mA
3.75mA
0mA
GLOBAL CURRENT = 0x00
FULL 7/8 6/8 5/8 4/8 3/8 2/8 1/8 ZERO
CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT
RAMP-UP
RAMP-DOWN
Figure 6. Output Fade DAC (Global Current = 0x07)
Maxim Integrated
Figure 7. Global Current Modifies Ramp-Down Behavior
21
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